Use of Unix tool "make"

The make utility is a software engineering tool for managing and maintaining computer programs. Make provides most help when the program consists of many component files. As the number of files in the program increases, compile time and complexity of compilation command also increases.

With make, the programmer specifies what the files are in the project and how they fit together, and then make takes care of the appropriate compile and link steps. Make can speed up your
compiles since it is smart enough to know that if you have ten .c files but you have only
changed one, then only that one file needs to be compiled before the link step. Make has
some complex features, but using it for simple things is pretty easy.

Simple Example

This is an example descriptor file to build an executable file called prog1. It requires the source files file1.cc, file2.cc, and file3.cc. An include file, mydefs.h, is required by files file1.cc and file2.cc. If you wanted to compile this file from the command line using C++ the command would be

% CC -o prog1 file1.cc file2.cc file3.cc

This command line is rather long to be entered many times as a program is developed and is prone to typing errors. A descriptor file could run the same command better by using the simple command

% make prog1

or if prog1 is the first target defined in the descriptor file

% make

Let's go through the example to see what make does by executing with the command make prog1 and assuming the program has never been compiled.

1. make finds the target prog1 and sees that it depends on the object files file1.o file2.o file3.o
2. make next looks to see if any of the three object files are listed as targets. They are so make looks at each target to see what it depends on. make sees that file1.o depends on the files file1.cc and mydefs.h.
3. Now make looks to see if either of these files are listed as targets and since they aren't it executes the commands given in file1.o's rule and compiles file1.cc to get the object file.
4. make looks at the targets file2.o and file3.o and compiles these object files in a similar fashion.
5. make now has all the object files required to make prog1 and does so by executing the commands in its rule.

Invoking make

Make is invoked from a command line with the following format

make [-f makefile] [-bBdeiknpqrsSt] [macro name=value] [names]

Frequently used make options

Command	Result
make	use the default descriptor file, build the first target in the file
make myprog	use the default descriptor file, build the target myprog
make -f mymakefile	use the file mymakefile as the descriptor file, build the first target in the file
make -f mymakefile myprog	use the file mymakefile as the descriptor file, build the target myprog